Do you need more stress (analysis) in your life?
Mentor Graphics is working on technology to analyze the effects of mechanical stress on integrated circuits, describing progress at the company’s U2U conference in San Jose this week (April 21). The...
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‘This sensor will self-destruct in the next five (hundred thousand) seconds’
Research by Professor John Rogers’ group at the University of Illinois is leading to biodegradable electronics, sparked partly by needs for systems that fall apart gradually after being discarded and...
View ArticleFinFET-project growth ‘stunning’ says EDA exec
Machine learning, smarter cars, and the infrastructure to support a sixfold increase in IoT and edge devices have helped push up the number of teams doing advanced-node designs, according to Tom...
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Cadence pulls Virtuoso and Allegro closer for 3DIC
Cadence Design Systems has brought its chip- and PCB-design environments closer together as the shift towards multichip packages gains pace. Cadence has made it possible to bring electrical models...
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Mentor builds links for multichip package integration
Mentor, a Siemens business, has formed an alliance with foundries and OSAT providers and launched a flow that brings IC and package design together. Keith Felton, marketing manager for the Expedition...
View ArticleEDA needs to work on the back end, says Qualcomm
It’s the back end that needs work as system-level considerations begin to dominate design, argued Qualcomm’s vice president of engineering in a short Visionary Talk on Wednesday at the Design...
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Design house recommends earlier start to flip-chip bump layout
Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout. The company said it has, through its turnkey programs for ASIC production,...
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Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become a JEDEC standard. Based on XML, the JEP181 standard lets tools share data on thermal behavior, easing the job of...
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Module verification demands integrated DRC and LVS
The trend toward combining multiple modules and chiplets within system-in-package (SIP) design poses major challenges for system-level verification, with a combined and integrated design rule check...
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Nvidia proposes split-level link for chiplet interconnect
Nvidia revealed at its Fall GTC work the company has done on a bidirectional energy-saving chiplet interconnect that could hit the equivalent of 50Gbit/s per line. In his talk on recent work performed...
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